FIGS. 6A and 6B show one phase of a circuit of a three-level inverter as disclosed in JP-A-2010-288415 (see particularly FIG. 3 in that reference, and the description thereof).
In FIGS. 6A and 6B, a direct current power source 1, may for example be a solar cell, and a voltage E thereof is divided into voltages E1 and E2 (normally, E1=E2) by capacitors 2 and 3 connected in series.
Semiconductor switches (hereafter also referred to simply as switches) 4 to 7, each formed of a MOSFET, can control a conduction/interruption of a forward current, and attain a conduction state always for a reverse current. The switches 6 and 7, connected in series in directions opposite to each other, configure a bidirectional switch which can control a conduction/interruption of both forward and reverse currents. Herein, the switches 4 and 5 are referred to as upper and lower arms, and a series circuit of the switches 6 and 7 as an intermediate arm, for the sake of convenience. An LC filter is configured of a reactor 8 and a capacitor 9, and the output terminals of the two ends of the capacitor 9 are interconnected to a power system 300 via a transformer 100.
A U point (an alternating current terminal) in FIGS. 6A and 6B attains the same potential as a P point by turning on the switch 4, an N point by turning on the switch 5, and an M point by turning on the switches 6 and 7 that configure a bidirectional switch. That is, the circuit can output three voltage levels by the switches 4 to 7 attaining an on-state, and has the characteristics that it is sufficient that the breakdown voltage of the switches 6 and 7 is ½ of that of the switches 4 and 5.
FIGS. 7A-7C show output voltage waveforms of the circuit, wherein an output voltage Vo is controlled to form a sine wave by causing the pulse train of a U-M voltage having the three voltage levels to pass through the LC filter.
When using the circuit of FIGS. 6A and 6B as an interconnection inverter for solar power generation, the voltage E of the direct current power source (solar cell) 1 fluctuates greatly in accordance with environmental conditions.
Meanwhile, the alternating current output voltage Vo is matched with a system voltage Vs by the transformer 100. The system voltage Vs fluctuates within a slight range, but is approximately constant, and as the transformer ratio of the transformer 100 is also constant unless a tap changing is carried out, it is necessary to keep the alternating current output voltage Vo at a substantially constant value proportional to the system voltage Vs.
The circuit of FIGS. 6A and 6B is one kind of voltage inverter, and as the alternating current output voltage Vo is controllable within a range in which the peak value thereof is equal to or less than a direct current input voltage, the positive peak of Vo is equal to or less than E1, and the negative peak is equal to or less than E2, as shown in FIGS. 7A-7C.
Consequently, Vo is taken to be a voltage which can be output even when E1 and E2 are minimum values within an operating range, and Vo is kept constant by determining the transformer ratio of the transformer 100 based on the size of Vo, and by widening the pulse width of PWM control when E1 and E2 are low (FIG. 7A) and narrowing the pulse width when E1 and E2 are high (FIG. 7B).
FIGS. 8A and 8B show a phase relationship between the alternating current output voltage Vo and a current I.
In the interconnection inverter for solar power generation, in order to supply power generated therein to the power system 300, a power factor 1 operation wherein the phase of the system voltage Vs, that is, the phase of the output voltage Vo is approximately coincident with the phase of the output current I, as shown in FIG. 8A, is carried out, but there is also a case in which by deliberately injecting reactive power, a polarity non-coincidence period Tc is created to reduce the power factor, as shown in FIG. 8B, thus carrying out a voltage adjustment at an interconnection point.
Current paths (1) to (4) shown in FIG. 6A previously described are in the cases of the power factor 1 in which the output voltage and the output current are coincident in polarity, wherein (1) and (3) are the paths in a voltage application period Ta in FIGS. 7A-7C, and (2) and (4) are the paths in a freewheeling period Tb.
When a direct current voltage is low, as in FIG. 7A, a time ratio at which the switch 4 or 5 conducts is high, and a conduction loss ratio in the upper and lower arms is high, in particular, in the vicinity of the peak of Vo. When the direct current voltage is high, as shown in FIG. 7B, a time ratio at which the switch 6 or 7 conducts is high, and a conduction loss ratio in the intermediate arm is high. When the direct current voltage is set so as to be always high using a voltage fluctuation compensation circuit to be described hereafter, as shown in FIG. 7C, a conduction loss ratio in the upper and lower arms is high in the same way as in FIG. 7A.
A shift from the path (1) to (2) in FIG. 6A is carried out by turning off the switch 4. Also, a shift from the path (2) to (1) is carried out by turning on the gate of the switch 7, turning off the gate of the switch 6 in advance, and after blocking a short circuit current in a path from the switch 4 through the switch 6 (the main body portion of the MOSFET) to the switch 7, turning on the gate of the switch 4. With the turning on of the switch 4, a reverse parallel diode of the switch 6 interrupts a current by reverse recovery. Shifts from the path (3) to (4) and from (4) to (3) are the same as above because the pairs of shifts are symmetrical operations. Consequently, in FIG. 6A, the switch 4 or 5 generates a turn-on loss or a turn-off loss, and the switch 6 or 7 generates a reverse recovery loss.
Meanwhile, paths (5) to (8) shown in FIG. 6B are in a case in which the output voltage and the output current are not coincident in polarity, wherein (5) and (7) are the paths in the voltage application period Ta in FIGS. 7A-7C, and (6) and (8) are the paths in the freewheeling period Tb. Without going into detail, in FIG. 6B, the switch 6 or 7 generates a turn-on loss and a turn-off loss, and the switch 4 or 5 generates a reverse recovery loss.
As in the above, in this heretofore known technology, the ratio of conduction losses, and the contents of switching losses, generated by respective semiconductor switches vary depending on operating conditions.